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PRELIMINARY
CY2282-1 CY2282-11S
100-MHz Pentium(R) II Clock Synthesizer/Driver with Spread Spectrum and USB for Desktop PCs
Features
* Mixed 2.5V and 3.3V operation * Clock Generator for Pentium(R) II, and other similar processor-based motherboards -- Two 2.5V CPU clocks at 66.6 or 100 MHz -- Seven 3.3V synch. PCI clocks, one free-running -- Two 3.3V 48 MHz USB clocks -- One 3.3V REF clock at 14.318 MHz -- One 2.5V APIC clock at 14.318 MHz or PCI/2 * Spread spectrum clocking for EMI control (CY2282-11S only) * Factory-EPROM programmable output drive and slew rate for EMI optimization * Low skew outputs, 175 ps between CPU clocks * Available in space-saving 28-pin SOIC package 3.3V USB clocks at 48 MHz, one 3.3V reference clock at 14.318 MHz, and one 2.5V APIC clock at 14.318 MHz. The CY2282-11S provides the same outputs as the CY2282-1 but also incorporates the Intel(R)-defined spread spectrum features. It provides a 0.5% downspread on the CPU and PCI clocks, which can improve EMI in certain high-speed systems. A summary of clock outputs for both devices is shown below. The CY2282 outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits, and factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control.
CY2282 Selector Guide
Clock Outputs CPU (66.6, 100 MHz) PCI (CPU/2, CPU/3 MHz) USB (48 MHz) APIC (14.318 MHz) REF (14.318 MHz) CPU-PCI delay Spread Spectrum
Note: 1. One free-running PCI clock.
CY2282-1 2 7[1] 2 1 1 1.5-4.0 ns None
CY2282-11S 2 7[1] 2 1 1 1.5-4.0 ns -0.5%
Functional Description
The CY2282 is a clock synthesizer/driver for a Pentium II, or other similar processor-based PC requiring 100-MHz support. The CY2282-1 outputs two CPU clocks at 2.5V. There are seven PCI clocks, running at one-half or one-third the CPU clock frequency of 66.6 MHz and 100 MHz respectively. One of the PCI clocks is free-running. Additionally, the part outputs two
Logic Block Diagram
APIC VDDAPIC XTALIN
XTALOUT
Pin Configuration
SOIC Top View
XTALIN XTALOUT VSS PCICLK_F PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 VDDUSB USBCLK0 USBCLK1 1 2 3 4 CY2282-1,-11S 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS REF VDDREF VDDAPIC APIC VDDCPU CPUCLK0 CPUCLK1 AVDD VSS NC NC SEL100 VSS
REF
14.318 MHz OSC. CPU PLL Divider STOP LOGIC
VDDREF CPUCLK [0-1] VDDCPU PCICLK_F
SEL100
EPROM
Delay STOP LOGIC
VDDPCI PCI [1-6] VDDPCI USBCLK [0:1] VDDUSB
SYS PLL
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 October 12, 1998
PRELIMINARY
Pin Summary
Name VDDPCI VDDUSB VDDREF VDDAPIC VDDCPU AVDD VSS XTALIN N/C SEL100 CPUCLK[0:1] PCICLK[1:6] PCICLK_F APIC REF USBCLK[0:1]
[2] [2]
CY2282-1 CY2282-11S
Pins 9 12 26 25 23 20 3, 15, 19, 28 1 2 17, 18 16 21, 22 5, 6, 7, 8, 10, 11 4 24 27 13, 14
Description 3.3V Digital voltage supply for PCI clocks 3.3V Digital voltage supply for USB clocks 3.3V Digital voltage supply for REF clocks 2.5V Digital voltage supply for APIC clocks 2.5V Digital voltage supply for CPU clocks 3.3V Analog voltage supply Ground Reference crystal input Reference crystal feedback No Connect. Can be driven HIGH or LOW. CPU frequency select input, selects between 100 MHz and 66.6 MHz (see table below) Internal pull-up to VDD CPU clock outputs PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz or 100 MHz respectively Free-running PCI clock output APIC clock outputs 3.3V Reference clock outputs USB clock outputs
XTALOUT
Function Table
SEL100 0 1 2 3 CPU/PCI Ratio CPUCLK 66.66 MHz 100 MHz PCICLK_F PCICLK 33.33 MHz 33.33 MHz REF 14.318 MHz 14.318 MHz APIC 14.318 MHz 14.318 MHz USBCLK 48 MHz 48 MHz
Actual Clock Frequency Values
Clock Output CPUCLK CPUCLK USBCLK Target Frequency Actual Frequency (MHz) (MHz) 66.67 100 48.0 66.654 99.77 48.008 PPM -195 -2346 167
Note: 2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
2
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5
CY2282-1 CY2282-11S
Storage Temperature (Non-Condensing) ... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Package Power Dissipation .............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together)
Operating Conditions[3]
Parameter AVDD, V DDPCI, VDDUSB, V DDREF VDDCPU VDDAPIC TA CL Description Analog and Digital Supply Voltage CPU Supply Voltage APIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK PCICLK APIC, REF USB Reference Frequency, Oscillator Nominal Value 14.318 Min. 3.135 2.375 2.375 0 Max. 3.465 2.625 2.625 70 20 30 20 20 14.318 MHz Unit V V V C pF
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Except Crystal Inputs[4] Except Crystal Inputs
[4]
Test Conditions
Min. Max. Unit 2.0 0.8 IOH = 12 mA CPUCLK IOH = 18 mA APIC IOL = 12 mA IOL = 18 mA CPUCLK APIC 2.4 V 2.0 0.4 V V V V
High-level Output Voltage VDDCPU = VDDAPIC = 2.375V Low-level Output Voltage VDDCPU = VDDAPIC = 2.375V
High-level Output Voltage VDDPCI, AVDD, VDDREF, VDDUSB = 3.135V IOH = 14.5 mA PCICLK IOH = 16 mA USBCLK IOH = 16 mA REF Low-level Output Voltage VDDPCI, AVDD, VDDREF, VDDUSB= 3.135V IOL = 9.4 mA PCICLK IOL = 9 mA IOL = 9 mA USBCLK REF
VOL
0.4V
V
IIH IIL IOZ IDD25 IDD25 IDD33
Input High Current Input Low Current Output Leakage Current Power Supply Current for 2.5V clocks Power Supply Current for 2.5V clocks Power Supply Current for 3.3V clocks
VIH = V DD VIL = 0V Three-state VDDCPU = 2.625V, V IN = 0 or V DD, Loaded Outputs, CPU = 66.6 MHz VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 100 MHz VDD = 3.465V, V IN = 0 or VDD, Loaded Outputs
-10 -10
+10 10 +10 70 100 170
A A A mA mA mA
Notes: 3. Electrical parameters are guaranteed with these operating conditions. 4. Crystal Inputs have CMOS thresholds.
3
PRELIMINARY
Switching Characteristics[5] Over the Operating Range
Parameter t1 t2 t2 t2 t4 t5 t6 Output All CPUCLK, APIC PCICLK USBCLK, REF CPUCLK CPUCLK CPUCLK, PCICLK PCICLK, PCICLK CPUCLK PCICLK CPUCLK, PCICLK Description Output Duty Cycle
[6]
CY2282-1 CY2282-11S
Test Conditions t1 = t1A / t1B Between 0.4V and 2.0V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 2.0V and 0.4V Measured at 1.25V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.25V Measured at 1.5V CPU, PCI clock stabilization from power-up
[7]
Min. 45 1.0 1.0 0.5 0.4
Typ. 50
Max. 55 4.0 4.0 2.0 1.8
Unit % V/ns V/ns V/ns ns ps ns
CPU and APIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate USB, REF Rising and Falling Edge Rate CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew
100 1.5
175 4.0
t7 t8 t9 t10
PCI-PCI Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
250 200 250 250 500 3
ps ps ps ms
Notes: 5. All parameters specified with loaded outputs. 6. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 7. PCI lags CPU.
Switching Waveforms
Duty Cycle Timing
t1A t1B
All Outputs Rise/Fall Time
VDD 0V t2 t3 t2 t4
OUTPUT
CPU-CPU Clock Skew
1.25V CPUCLK
CPUCLK t5
1.25V
4
PRELIMINARY
Switching Waveforms (continued)
CPU-PCI Clock Skew
CPUCLK 1.25V
CY2282-1 CY2282-11S
PCICLK t6
1.5V
PCI-PCI Clock Skew
1.5V PCICLK
PCICLK t7
1.5V
5
PRELIMINARY
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
CY2282-1 CY2282-11S
Application Circuit
XTALIN XTALOUT Cx APIC CPUCLK PCICLK_F PCICLK REF USBCLK Rs APIC CPUCLK PCICLK_F PCICLK REF USBCLK
SEL100
SEL100
Cd 0.1F
VDDPCI VDDREF VDDUSB AVDD
VDDAPIC VDDCPU Cd 0.1F VSS CY2282-1,-11S 28 PIN SOIC Cd = DECOUPLING CAPACITORS Ct = OPTIONAL EM-REDUCING CAPACITORS Cx = OPTIONAL LOAD MATCHING CAPACITOR Rs = SERIES TERMINATING RESISTORS Ct
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > Rtrace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F-22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
6
PRELIMINARY
CY2282-1 CY2282-11S
Test Circuit
VDDPCI, AVDD, VDDUSB, VDDREF
3, 15, 19, 28 9, 12, 20, 26 0.1 F CY2282-1, -11S
VDDCPU, VDDAPIC 23, 25 0.1 F
OUTPUTS CLOAD
Notes: Each supply pin must have an individual decoupling capacitor All capacitors must be placed as close to the pins as is possible.
Ordering Information
Ordering Code CY2282SC-1 CY2282SC-11S Document #: 38-00693-A Package Name S21 S21 Package Type 28-Pin SOIC 28-Pin SOIC Operating Range Commercial Commercial
Package Diagram
28-Lead (300-Mil) Molded SOIC S21
51-85026-A
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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